1. Field of the Invention
The present invention relates to a pulse width modulator, more specifically, it relates to a pulse width modulator which is, particularly, used preferably in controlling a DC motor, wherein the pulse width of the output signal changes slowly when a pulse width of an output signal is controlled to change.
2. Description of the Prior Art
As a pulse width modulator used in controlling a DC motor, a so-called PWM (Pulse Width Modulation) modulator, or a PPM (Pulse Position Modulation) modulator and the like are practically used as the prior art.
FIG. 1 is a block diagram showing a general configuration of an 8-bit PWM modulator as one example of such prior art.
In FIG. 1, numeral 1 designates a data bus connected to a CPU 21 which is a control center of an entire PWM modulator.
Numeral 2 designates an 8-bit timer register as first storing means, and 8 bits in the data bus 1 are connected thereto via a signal line 51. An 8-bit set value outputted to the data bus 1 from the CPU 21 is stored in the timer register 2.
Numeral 3 designates an 8-bit waveform timer as second timing means. The waveform timer 3 is connected to the above-mentioned timer register 2 through a signal line 52 provided with a gate 41 in the midway thereof. When the gate 41 is opened, the 8-bit set value stored in the timer register 2 is loaded as count data. While, a count clock serving as a source clock is inputted to the waveform timer 3 via a signal line 60, thereby the count clock is counted down with a value loaded from the timer register 2 as an initial value of the count data, and a count value is outputted to a waveform timer overflow control circuit 4 via a signal line 54. However, the waveform timer 3 starts its counting operation when a count start trigger is given from a cyclic timer overflow control circuit 6 to be described later via a signal line 56.
As stated above, the waveform timer overflow control circuit 4 inputs the count value of the waveform timer 3 given from the waveform timer 3 via the signal line 54, and when the value overflows, or specifically, when it becomes "00H" (H represents a hexadecimal number), outputs a waveform trigger signal to a waveform generating circuit 5 being a waveform generating means via a signal line 55.
The waveform generating circuit 5 generates a PWM output waveform as an output signal of a PWM modulator whose entire configuration is shown in FIG. 1, and outputs it to the outside via a signal line 58. Specifically, when the waveform trigger signal is given from the waveform timer overflow control circuit 4 via the signal line 55, the waveform generating circuit 5 outputs an "L" level signal thereafter, and when the waveform trigger signal is given from the cyclic timer overflow control circuit 6 to be described later via a signal line 57, outputs an "H" level signal thereafter.
In other words, the waveform generating circuit 5 changes the PWM output waveform into "L" level when the waveform trigger signal is given from the waveform timer overflow control circuit 4, and changes the PWM output waveform into "H" level when the waveform trigger signal is given from the cyclic timer overflow control circuit 6.
Numeral 7 designates an 8-bit cyclic timer as first timing means, to which is inputted the count clock via the signal line 60 in the same way as the waveform timer 3. The cyclic timer 7 repeats the down counting operation of the count clock from "FFH" to "00H", and outputs the count value to the cyclic timer overflow control circuit 6 via a signal line 59.
When the count value of the cyclic timer 7 inputted via the signal line 59 becomes "00H", the cyclic timer overflow control circuit 6 outputs the waveform trigger signal to the waveform generating circuit 5 via the signal line 57, the count start trigger signal to the waveform timer 3 via the signal line 56, and an input control signal of count data to the gate 41 via the signal line 53.
The gate 41 is provided so as to load the set value of the timer register 2 to the waveform timer 3 as the count data as stated above. As stated above, the gate 41 is opened and closed by the input control signal of the count data given from the cyclic timer overflow control circuit 6 via the signal line 53.
Next, the operation of a conventional PWM modulator having the aforementioned configuration is described.
In a state where the PWM modulator is not operating, the gate 41 which controls the count data input to the waveform timer 3 is opened, thus when the CPU 21 writes set value data into the 8-bit timer register 2 from the data bus 1 via the signal line 51, the set value is stored in the 8-bit waveform timer 3 as count data via the signal line 52.
Now, for example, it is assumed that "55H" is written into the timer register 2 as an initial value of the count data of the waveform timer 3.
When the PWM modulator is started after writing the count data into the waveform timer 3, it starts simultaneously with the 8-bit cyclic timer 7. The waveform timer 3 counts down the count clock signal inputted via the signal line 60, from the initial value "55H" of the count data. "FFH" is written into the 8-bit cyclic timer 7 as the initial value, and the count clock signal inputted via the signal line 60 is counted down.
FIG. 2 is waveform diagrams showing an operating state of a PWM modulator.
Symbol WF1 designates a count clock, WF2 designates a count value of a cyclic timer 7, WF3 designates a count value of a waveform timer 3, WF4 designates a waveform trigger signal outputted from a cyclic timer overflow control circuit 6, WF5 designates a waveform trigger signal outputted from a waveform timer overflow control circuit 4 and WF6 designates a PWM output waveform outputted from a waveform generating circuit 5. In addition, symbol OF represents an overflow cycle of a cyclic timer 7, or one cycle of a PWM waveform.
It is assumed that the PWM output waveform at the time point of starting of the PWM modulator is at "H" level as shown by WF6 in FIG. 2. The waveform timer 3 and the cyclic timer 7 have started simultaneously, however, the count value of the waveform timer 3 becomes "00H" first as shown by WF3 in FIG. 2. Though the waveform timer 3 stops to operate when its count value becomes "00H", the waveform timer overflow control circuit 4 out, puts the waveform trigger signal to the waveform generating circuit 5 via the signal line 55 as shown by WF5 in FIG. 2. The waveform generating circuit 5 receiving the waveform trigger signal from the waveform timer overflow control circuit 4, inverts the PWM output waveform which has been at, "H" level and outputted to the signal line 58, into "L" level as shown by WF6 in FIG. 2.
Thereafter, when the count value of the cyclic timer 7 becomes "00H" as shown by WF2 in FIG. 2, the cyclic timer overflow control circuit 6 outputs the waveform trigger signal to the waveform generating circuit 5 via the signal line 57 as shown by WF4 in FIG. 2, and outputs a signal opening the gate 41, through which count data of the waveform timer 3 is inputted via the signal line 53.
Thereby, a value stored in the timer register 2 is again inputted to the waveform timer 3.
Also, the cyclic timer overflow control circuit 6 simultaneously outputs a start signal to the waveform timer 3 via the signal line 56. The waveform timer 3 starts to operate in synchronism with the cyclic timer 7 so as to coincide with the timing at the starting time of the PWM modulator .
While, the waveform generating circuit, 5 which has received the waveform trigger signal from the cyclic timer overflow control circuit. 6, inverts the PWM output waveform, having been at "L" level and outputted to the signal line 58, into "H" level as shown by WF6 in FIG. 2.
By repeating the above-mentioned operations, a waveform whose period of "one cycle.times.55H of the count clock" becomes the "H" level, and period of "one cycle.times.ABH of the count clock" becomes the "L" level with the period shown by OF in FIG. 2 as one waveform cycle, is outputted repeatedly.
While, when the set value of the timer register 2 is changed during the operation of the PWM modulator, since the gate 41 opens and a new set value is inputted to the waveform timer 3 as count data at the time point when the cyclic timer 7 has overflown, the length of "H" level period of the PWM waveform changes from the next cycle.
FIG. 3 is a waveform diagram showing changes of waveforms when changing the value of the timer register 2. In FIG. 3, the same reference numerals as in FIG. 2 designate the same signal waveforms. Here, in FIG. 3, WF8 shows the set value of the timer register 2 and .phi. represents one cycle of the count clock.
When the set value of the timer register 2 changes, for example, to "40H" from "55H" as shown by WF8 in FIG. 3 during the operation of the PWM modulator, "40H" is inputted to the waveform timer 3 as count data at the next overflow timing of the cyclic timer 7. And, a wave for whose period of "one cycle.times.40H of the count clock" of the output waveform of the waveform generating circuit 5 becomes the "H" level from the next waveform cycle, and whose period of "one cycle.times.C0H of the count clock" becomes "L" level is outputted.
In the conventional pulse width modulator, since a change of a value of the register which sets the ratio of the "H" level period and the "L" level period of the output waveform is immediately reflected to the output waveform, it is necessary to change the set value of the register little by little in multisteps, when the number of revolutions is to be changed slowly at the time of controlling a DC motor, resulting in a heavy burden of softwares.